The present invention relates to managing clock skew when separate clock meshes are employed to provide different clock frequencies to different portions of a large scale integrated (LSI) circuit.
A system clock signal is often used by digital circuitry, such as digital circuitry implemented using a LSI circuit, to synchronously execute certain logic functions. For example, ultra-deep sub-micron (UDSM) microprocessors employ digital circuitry that use system clock signals to synchronously execute logic functions. These microprocessors operate at system clock frequencies of 1 GHz and higher. The system clock signal of a given LSI circuit is often split into many paths to service many different portions of the digital circuitry. Ideally, the system clock signals at different portions of the digital circuitry exhibit exactly the same timing characteristics so that the different portions of the digital circuitry operate in exact synchronization. In practice, however, the system clock signals at various points throughout the digital circuitry exhibit differing timing characteristics, such as differing rising and/or falling edges (i.e., transitions), differing duty cycles, and/or differing frequencies. These non-ideal characteristics are often referred to as clock jitter and clock skew.
Clock jitter relates to the inaccuracies inherent in generating the system clock signal. The non-ideal characteristics of the system clock signals due to clock jitter affect all portions of the LSI circuit in the same way, irrespective of how the system clock signals are distributed to those portions of the circuit. Clock skew relates to the inaccuracies introduced into the system clock signals by the distribution technique employed to split the system clock into many paths and deliver the clock signals to different portions of the digital circuit.
Sources of clock skew may be classified as being statically occurring or dynamically occurring. Statically occurring sources of clock skew are caused by the LSI design or manufacturing process irrespective of the operating conditions of the LSI circuit. Dynamically occurring sources of clock skew are caused by the operating conditions of the LSI circuit, which may also be functions of the LSI circuit design or manufacturing process.
Statically occurring sources of clock skew include (i) variations in transistor load capacitance (e.g., gate load capacitance); (ii) RC delay of circuit interconnections (e.g., the asymmetry of wire lengths and widths); (iii) variations and/or asymmetries in cross-coupling capacitance between wires (e.g., inter-wiring capacitance); and (iv) semiconductor process variations (e.g., transistor threshold voltage variations, transistor ON resistance variations, wiring variations, vias, and contact RC variations).
Dynamically occurring sources of clock skew include (i) cross-coupling between wire lengths due to inter-wiring capacitance; (ii) cross-coupling between wire lengths due to inductive coupling; (iii) cross-coupling due to return path current; (iv) temperature variations; and (v) variations in VDD and VSS (e.g., DC operating voltage variations).
Unfortunately, the variations in the timing characteristics of the system clock signals due to clock skew result in undesirable errors in the operation of the digital circuitry of the LSI circuit. The problem is exacerbated as the size (i.e., number of logic gates and corresponding circuit area) increase and/or as the clock signal frequency increases.
Various techniques have been developed and employed to ameliorate the undesirable affects of clock skew. These techniques include (i) utilizing clock bars (i.e., relatively wide bars to carry the system clock to various portions of the LSI circuit); (ii) RC delay balancing (i.e., wiring techniques that focus on wiring geometry to match RC delay characteristics); (iii) utilizing a grid structure in distributing the system clock signal; (iv) utilizing a hierarchical structure in partitioning the LSI circuit into regions; (v) utilizing active feedback in compensating the system clock signal; (vi) utilizing local oscillators in various regions of the LSI circuit and an overall resonance for the LSI circuit; and (vii) utilizing the resonances of wiring loops. For various reasons, these techniques have not been adequately successful in addressing the undesirable problems caused by clock skew.
FIG. 1 is a schematic diagram of a circuit 100 in which a single clock signal is distributed to a clock mesh 106 via a clock tree 104 employing a conventional approach. After the signal emerges from the PLL (Phase-Locked Loop), OSC (Oscillator) or other clock source 102, the signal branches off along several possible paths within clock tree 104 before reaching clock mesh 106. A plurality of clock buffers 108 are used to fan the clock signal out to multiple points on the clock mesh 106. Various points in circuit 100 will experience clock skew for all the reasons discussed above.
FIG. 2 is a schematic diagram of a circuit 200 in which two separate clock signals, at different frequencies, are distributed to respective meshes 206 and 216 along separate respective clock trees 204 and 214. The clock skew problem is exacerbated when separate clock trees and separate clock meshes are employed to deliver different clock frequencies to different portions of a circuit.
FIG. 2 illustrates a conventional approach for implementing a 4-GHz (gigahertz) clock mesh 206 and a 2 GHz clock mesh 216. Circuit 200 accomplishes this by providing a ½ frequency divider 212 coupled to the output of 4 GHz oscillator 202 and by providing separate clock trees 204, 214 to deliver the 4 GHz and 2 GHz clock signals, respectively, to the 4 GHz clock mesh 206 and the 2 GHz clock mesh 216, respectively. Employing this configuration, the point of synchronization between the two signals is located where the 4 GHz signal is directed to the frequency divider 212 to generate the 2 GHz signal. From that point onward, as the signals propagate along their respective clock trees toward their respective clock meshes, clock skew will generally become progressively worse as each length of wire and each device through which each signal travels introduces another opportunity for disparities in the speed of propagation of the respective signals to arise.
FIG. 3 is a timing diagram illustrating clock skew occurring within the circuit of FIG. 2. Graph 302 is a plot of the 4 GHz signal at the output of the oscillator 202. Graph 304 is a plot of the 2 GHz signal generated from the 4 GHz signal at the output of the ½ frequency divider 212, under ideal conditions. Graphs 306 and 308 illustrate 2 GHz clock signals that may appear at different points in the clock mesh 216. Clock skew for the 2-GHz signals, illustrated by graphs 306 and 308, with respect to the 4 GHz signal illustrated by graph 302 is apparent.
Conventional techniques for reducing the resulting clock skew between separate meshes are very complex. Accordingly, there is a need in the art for a simpler solution to the problem of clock skew between clock meshes operating at different frequencies.